ic manufacture wafer production

IC Manufacture, Steps & Raw Material

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The structure of the IC is very complex both in terms of surface topography and its internal composition. Each element in a device has a three-dimensional architecture that must be produced equally for each series. Each component is a structure consisting of many layers, each of which has a specific pattern. Some layers are embedded in silicon and some are piled on top of it. The IC manufacturing process requires an exact work order and careful circuit design is needed.

At this time, an IC can contain millions of components. These components are so small that the whole circuit only occupies an area of ​​less than 1 cm2. Silicon crystal wafers as the starting material, with a diameter of about 10 cm to 30 cm so that on the surface of the wafer can be made tens to hundreds of complete circuits. For mass production even hundreds of wafers can simultaneously be used in a manufacturing process simultaneously. Of course this is very beneficial in terms of the costs and energy used. However, before reaching the level of mass production, a series of testing processes for various production steps must be carried out carefully. Broadly speaking, the process of making wafer crystal silicon can be explained by the following picture:

IC CHIP SEMICONDUCTOR MANUFACTURING PROCESS

Initially, crystalline silicon wafers were produced by the IC manufacturer until the circuit was made on it. But now almost all IC manufacturers buy crystal wafer silicon from third parties (suppliers).

 

IC Manufacturer

Currently the IC factory or lab has developed a lot, including MOSIS in the USA, TMC in Taiwan, TIMA in France, NEC in Japan, Samsung in Korea, MIMOS in Malaysia, and many others. Generally these companies begin the process of Wafer Fabrication, which is the process of making a circuit on a wafer crystal silicon that is still intact.

 

1. Wafer Fabrication

Wafer Pabrication

A. Cleaning

Silicon wafers must always be clean (not contaminated with organic or metal particles) at each stage of the Wafer Fabrication process. The most widely used is the RCA Clean method.

B. Oxidation

One of the main reasons why silicon is most widely chosen as a semi-conductor is because silicon offers a variety of conveniences, including the ease of forming a high-quality insulator layer on its surface through an oxidation process. That is the chemical reaction between silicon and oxygen or water vapor at temperatures between 1000°C – 1200°C so that it forms a layer of Silicon Dioxide (SiO2) on the surface of the wafer. SiO2 is stable at high temperatures and is one of the best insulators.

C. Photolithography

Photolithography is the main process in Wafer Fabrication, where microscopic patterns that have been designed are moved from the mask to the wafer surface in the form of a real circuit. Beginning with giving a layer of photoresist (photosensitive chemical liquid) on the surface of the wafer.

Then on the photoresist coated silicon wafers placed on a mask / reticle in the form of a transparent glass slab which has been filled with a similar circuit (die) to be made, then exposed to UV light so that the photoresist layer on the surface of the wafer exposed to UV light will easy to peel with the help of special chemical liquids.

So on the wafer surface there will be a circuit pattern like a pattern on a mask / reticle.

D. Ion Implantation

In the IC manufacturing process, this stage is a stage that requires special control. Ion implantation is the process of implanting an impurity atom (ion) into a silicon wafer which is not covered by the photoresist layer with the help of electric voltage (to regulate ion penetration depth) and electric current (to regulate the number of ions) silicon wafers.

This ion implantation technique is more widely used even though there are actually other techniques for implanting impurity atoms into silicon wafers called Difussion techniques, which are techniques for implanting atoms (dopants) on silicon wafers to change the resistivity properties with the help of high temperatures between 1000°C – 1200°C. This diffusion process is similar to the process of propagating ink which is dropped on a glass of clear water. When the silicon wafer is released from high temperatures to room temperature, the atom that propagates will stop propagating (in its last position).

E. Etching

In the early years of the development of IC technology, the etching technique used was Wet Etching by using a chemical liquid that was able to spread in all directions equally (isotropic) to shed the SiO2 layer on the surface of the silicon wafer. The disadvantage is that part of the SiO2 layer, which is just below the photoresist layer, also partially decays, so it will be a problem if the pattern is very thin.

Along with the development of IC technology which then uses other materials such as Silicon Nitride (Si3N4) and Polysilicon where both of these materials cannot use the Wet Etching technique, the Wet Etching technique is currently abandoned. Instead, the Dry Etching technique that uses gas (flourine, chlorine and bromine) is introduced which has an anisotropic effect, namely the ability to shed with a penetration speed that is not equal.

F. Chemical Vapor Deposition (CVD)

At low pressure and a certain temperature gas or chemical vapor will react to the film layer on the surface of the silicon wafer

Ammonia (NH3) and Dichlorosilane (SiHCl2) gas will react to produce a solid Silicon Nitride (Si3N4) film with a thickness of only a few microns or a few nanometers. While the remaining reaction gases are Hydrogen Chloride (HCl), Chlorine (CL2), Hydrogen (H2) and Nitrogen (N2) will be pumped out of the reactor.

G. Sputter Deposition

Although in general the CVD process is superior to sputtering but not all metals needed in the IC manufacturing process can be formed on the surface of silicon wafers. The sputtering process utilizes an electric field to take positive Argon ions to form a thin metal layer (film) on the target on the surface of the silicon wafer.

H. Chemical Mechanical Planarization (CMP)

CMP is a combination of the use of chemical methods (to soften first the layer of material to be removed) and mechanical (rubbing with polishing slurry) to remove materials that are not needed on the surface of silicon wafers so that only the materials needed (according to the design) are still attached to the surface of the wafer.

Of all the processes described above and combined with many other processes, one of them is Metallization (to connect all the components contained (resistors, capacitors, transistors etc.) so as to form a series of ICs that are in accordance with the design that has been planned), then the end result is a number of ICs (die) that still blend into a silicon wafer.

 

2. Wafer Test

The die produced in the Wafer Fabrication process is not 100% functioning properly. To find out which die is damaged, initial testing is required. Each type of die produced has its own testing device called a probe card. This special tool is made specifically for each different type of die, but all of them are equipped with small needles designed in such a way that it fits the position of the bond pad on the die to be tested.

The wafer silicon to be tested is then clamped on a clamping device on the Prober Wafer. Wafer Prober is fully controlled by the Tester, which is a computerized system that can be programmed automatically to drive the Probe Card to test various electrical properties on each die found on the surface of the silicon wafer then mark each die that is not functioning properly (damaged).

 

3. Packaging

IC Silicon, which is in the form of die, needs careful handling because it is easily broken even though it has been given a special protective layer. In addition, the bond pad has a very small size so it is very difficult to connect with other components in a series of electronic applications.

To protect the die and to facilitate handling and connection with other electronic components, packaging / packaging is needed.

  1.  Silicon wafers that have been tested are placed on a blue tape that is spread on metal whose surface is flat with the back that has no circuit attached to the surface of the blue tape. Then proceed with cutting the wafer silicon into die pieces using a special high-speed (diamond-edged) knife. The die pieces will remain attached to the surface of the blue tape.
  2.  A good die cut (has passed the initial test) is removed from the blue tape and transferred to the leadframe (a component made of copper that functions as the legs of the IC) and glued with epoxy then heated so that the epoxy hardens and the die is inseparable from leadframe. The process of extracting from blue tape and transferring it to the leadframe is done automatically by the engine.
  3.  Wirebonding, which is the process by which the leadframe legs are connected to the bond pad on the die using gold wire. This work is also done by the engine automatically
  4.  Molding, which is to close the leadframe by using a compound pressed at a certain temperature and air pressure so that the die and gold thread that was originally open will be covered by a compound.
  5. Solder Platting, which is the process of plating the feet of the IC with tin so that the legs made of copper are silver.
  6. Marking, which is the process of labeling the type of IC, part number, company name, date and so on to facilitate further identification.

The molding technique as described above, causes the outer packaging of the IC to be larger than the die size in it. In effect, the high frequency signal from the IC is slightly disturbed. To overcome this weakness, technology has now been developed that makes it possible to produce ICs with packaging sizes that are almost as large as the die size in them. This technique has also succeeded in improving the high frequency signal quality. The technique is named Flip Chip.

In this technique, first a bond pad is made which is a pair for connecting pad contained in the die to be packed. Then in the prepared bond pad, tin is formed which forms bumps. After all the bond pad is filled with bump, then it is paired with the connecting pad on the die and then heated so that both are joined by melting tin.

 

4. Final Test

During the packaging process there is a possibility that the die will be damaged or the packaging process is not perfect. The final test is carried out on all ICs that have been finished packed with the aim that the IC which is damaged during the packaging process is not sent together with a good IC. The final test method is almost the same as the initial test of silicon wafers, the difference is that the finished IC does not require a Prober Wafer anymore but uses a Handler. The handler is also fully controlled by the Tester to test various electrical properties in each IC while sorting through the quality of each IC.

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